Deep submicron (DSM) complementary metal oxide semiconductor (CMOS) circuits make extensive use of interconnects and contacts, and these latter features must be scaleable as well to ensure smooth migrations to smaller geometries. Connections to and between active CMOS FET devices are typically created with so-called “silicide” contacts, in which a portion of a source/drain region is converted during a thermal treatment into a metallic low resistance region. Silicidation reactions are well-known, and state of the art manufacturing processes in the 0.18 micron realm typically utilize some form of TiSi2 material as a gate and active region contact. However TiSi2 has several limitations, including linewidth-dependent sheet resistance, low thermal stability, and the fact that titanium can consume an unpredictable amount of silicon during the salicidation reaction. Such characteristics severely handicap the potential for TiSi2 in next generation technologies.
Cobalt silicide (CoSi2) has recently been advocated as a replacement for TiSi2.
One example of a prior art technique disclosing the making and use of CoSi2 is Goto et. al. “Optimization of Salicide Process for sub 0.1 um CMOS Devices” 1994 Symposium on VLSI Technology Digest of Technical Papers, page 119. Cobalt, however, is not without its limitations and problems as well. For instance, Cobalt is sensitive to oxygen and water. Even using very high purity inert gas for the heat treatment, the resulting cobalt salicide is often oxygen contaminated and a sheet resistance of the cobalt salicide thus increases. To prevent such oxidization of the cobalt layer, Goto discloses a cobalt salicide process using a Ti or TiN cap layer on top of the cobalt layer. Thus, a cobalt layer is deposited on a wafer having a top surface comprised of a mixture of exposed surfaces, including dielectric (typically sidewall and isolation) surfaces and silicon surfaces (typically gate and source/drain regions). A Ti or TiN cap layer is deposited on the cobalt layer without exposing the cobalt layer to air. The wafer is then subjected to a first anneal. During the first anneal cobalt reacts with silicon at the surface of the wafer where silicon contacts with cobalt. After the first anneal the wafer is etched in a NH4OH, H2O2, HO2 solution and then with a HCl, H2O2, HO2 solution. This two-step wet process etches away any metals which are not silicided, that is, Co, Ti, TiN and mixtures thereof. The wafer is then subjected to a second annealing process. In this process conventional semiconductor process quality N2 can be used during the first annealing. After this first anneal the Ti or TiN cap prevents residual oxygen from reacting with Co; therefore the resistance of the produced cobalt salicide does not increase due to an oxygen contamination problem.
As mentioned earlier, to prevent oxidation during silicidation, Ti and TiN are most widely used for capping a Co layer in the Co salicide process. The two materials have different strengths and weaknesses in this regard. For instance, TiN is more stable and does not react much with the Co layer. Nonetheless, Ti is more favored at this time, in large part because Ti is more reactive toward oxygen, and therefore is a potentially a better cap for preventing oxidation of Co. A Ti cap is also known to produce a more thermally stable Co salicide film. This fact is disclosed in Sohn et al. “Effects of Ti-capping on formation and stability of Co silicide” Journal of The Electrochemical Society 147 (1) page 373-380, 2000.
The use of Ti capping on Co however results in a complicated silicidation reaction. As Sohn points out, during the first anneal, Si reacts with Co to form a CoSix layer, consisting of primarily CoSi and CoSi2; Ti diffuses into the Co layer as Co reacts with Si; the Co and Ti form a layer of intermetallic mixture and the Ti layer experiences some nitridation. All these reactions take place in the same time causing complex process control consequences. This phenomenon is illustrated generally in FIG. 14.
In addition, for a Ti capped Cobalt silicide process, the first anneal temperature typically needs to be higher than for a comparable TiN capped process. This is a result of the effect of Ti diffusion into the Co layer and the resulting mediation of the silicidation reaction by Ti. In other words, in a Ti-mediated cobalt silicidation process, the presence of Ti retards the Co—Si reaction so that higher anneal temperatures are needed to complete the total reaction. According to Sohn, Ti diffuses into the Si interface and silicide grain boundary, thus stabilizing the final CoSi2 film,. Not all deposited Co reacts to form silicide because some Co reacts with the Ti and is converted into a Co—Ti intermetallic mixture layer. Usually in conventional processes, a Ti cap of 1 to 2 times the thickness of Co is used. Using such a large amount of Ti in turn affects the amount of Co that can ultimately react with silicon. All of these effects are hard to predict and control and this makes the task of process engineering with cobalt silicide quite complicated. For instance, the final thickness of Cobalt silicide needs to be precisely controlled for more advanced generation of process because of the scaling down of source and drain junction depth.
Thus, although the conventional Co salicide process generally meets the requirement of advanced process of less than 0.1 um feature size, there is need to further improve the Co salicide process, and to ensure that it will be useable even below such feature size. There is a substantial need in the industry to have an extremely small feature size/line width Co silicide process that achieves such scaled down thicknesses yet has good thermal stability to withstand anneal temperature near 800 to 900 degrees centigrade without agglomeration. Furthermore, there is a need to be able to control the process with a better process margin, especially as pertains to the thickness and the sheet resistance of the Co silicide film. Finally, there is an additional pressing need for a basic process flow and process tool for forming Co salicide that achieves a higher productivity in conventional semiconductor manufacturing.